1. Field of the Invention
This invention relates to a duty adjustment circuit which adjusts the duty ratio of a clock signal to a desired value.
2. Description of the Related Art
Japanese Patent Kokai (Laid-open Application) No. 10-163823 discloses a conventional duty ratio correction circuit. In the following, the same reference numerals and symbols as used in Japanese Patent Kokai No. 10-163823 are used with parentheses for easier understanding of this prior art. This duty ratio correction circuit includes a first CR integration circuit (101) to integrate a clock signal (CKI) with a time constant (T1) shorter than a half-period thereof. The duty ratio correction circuit also includes a second CR integration circuit (102) to integrate the same clock signal (CKI) with another time constant (T2) substantially longer than the period thereof. The duty ratio correction circuit compares the output signals of the CR integration circuits (101) and (102) using a comparator (16) and outputs the comparison result as a duty ratio correction clock signal (CKO).
In this duty ratio correction circuit, the output signal of the comparator (16) is fed back to the input side via a feedback resistance, and added to the output signal of the second CR integration circuit (102). Accordingly, the comparator (16) acquires a hysteresis characteristic, so that noise of amplitude smaller than this hysteresis can be excluded. When the duty ratio of the input clock signal (CKI) is not 50%, the output voltage of the first CR integration circuit (101) and the output voltage of the second CR integration circuit (102) tend toward the same level, so that the duty ratio of the duty ratio correction clock signal (CKO) generated as the result of comparison of these output voltages is improved and approaches 50%.
However, when noise of amplitude greater than the hysteresis (e.g., high-level instantaneous noise due to electrostatic discharge or other causes) is applied to the above described duty ratio correction circuit, this duty ratio correction circuit cannot exclude the noise, so that a clock signal with an extremely short pulse width is generated. As a result, in a circuit which receives the clock signal, there is the possibility of erroneous operation or of entering an inoperable state.